The present invention relates to an image sensor, and more particularly, to an image sensor with high resolution, high performance and small pixel sizes. For this purpose, the present invention provides a pixel having a vertical blooming control structure, one address line and one column output line per pixel without having additional charge transfer and reset lines. The present invention also provides a pixel having an integrated bipolar transistor gain stage where charge received from a pinned diode is multiplied several times before a signal is transferred on a common column output line and processed by a current sensing column correlated double sampling (CDS) circuit.
Typical image sensors sense light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. After completion of the integration cycle, collected charge is converted into a voltage, which is supplied to an output terminal of the sensor. In a typical complementary metal-oxide semiconductor (CMOS) image sensor, the charge-to-voltage conversion is accomplished directly in pixels and an analog pixel voltage is transferred to an output terminal through various pixel addressing and scanning schemes. An analog signal may be converted on-chip to a digital equivalent before reaching a chip output. The pixels have incorporated in them a buffer amplifier, typically a source follower, which drives sense lines that are connected to the pixels by suitable addressing transistors. After the charge-to-voltage conversion is completed and the resulting signal transferred out from the pixels, the pixels are reset in order to be ready for accumulation of new charge. In a pixel that uses a floating diffusion (FD) node as a charge detection node, the reset is accomplished by turning on a reset transistor that momentarily conductively connects the FD node to a voltage reference. This step removes the collected charge; however, it generates kTC-reset noise as is well known in the art. The kTC-reset noise has to be removed from a signal by a correlated double sampling (CDS) signal processing technique in order to achieve desired low noise performance. The typical CMOS image sensor that utilizes the CDS concept needs, to have four transistors (4T) per pixel. An example of the 4T pixel circuit can be found in U.S. Pat. No. 5,904,493 issued to Lee et al. in the name of “Active Pixel Sensor Integrated With A Pinned Photodiode.”
FIG. 1 illustrates a simplified cross-sectional view of a conventional complementary metal-oxide semiconductor (CMOS) image sensor pixel with a pinned photodiode and an associated pixel circuit. A P-type silicon-based substrate 101 disposed on a P+-type substrate 123 has a shallow trench isolation (STI) region 102 etched in a surface of the P-type substrate 101 and filled with a silicon dioxide layer 103. The silicon dioxide layer 103 also covers the remaining surface of the P-type substrate 101. A shallow P-type doping region 104 passivates walls and a bottom of the STI region 102 as well as the surface of the P-type substrate 101. Photo-generated charge is collected in an N-type doping region 105 of the pinned photodiode.
When the charge integration cycle is completed, the charge from the N-type doping region 105 is transferred to a floating diffusion (FD) region 106 by turning a gate 107 momentarily on. A first transistor 118 resets the FD region 106 to a suitable potential (e.g., approximately the power supply voltage (Vdd) level), and a second transistor 114 senses the FD potential change. A capacitor 119, which is also labeled as Cs in FIG. 1, is connected between a first node 117 in a Vdd line and a second node 113 connected to the FD region 106, and is used to adjust a conversion gain of the pixel. This capacitor 119 can be omitted from the circuit if necessary. The pixel is addressed via a third transistor 115. Herein, the gate 107 may be a gate of a transfer transistor, and the first and third transistors 118 and 115 may be reset and selection transistors, respectively.
Multiple control signals are supplied to the pixel via transfer gate, reset gate and address gate buses 112, 120 and 121, which are also labeled respectively as Tx, Rx and Sx in FIG. 1. An output of the pixel is supplied to a pixel column bus 116. When photons 122 impinge on the pixel, the photons 122 penetrate into the silicon bulk (i.e., the P-type substrate 101 and the P+-type substrate 123) depending on the wavelength of the photons 122 and create electron-hole pairs. Electrons are generated in depletion and undepletion regions of the silicon bulk. Reference numeral 108 represents the depletion region. Those electrons 110 generated in the undepletion region diffuse to a boundary 109 of the depletion region 108 in which the electrons 110 are quickly swept into a potential well located in the N-type doping region 105. Those electrons 110 generated in the neutral undepletion region can also diffuse laterally and may contribute to a pixel crosstalk. For this reason, the depletion region 108 is formed to a depth Xd suitable for the minimization of the pixel crosstalk.
Since such a high performance pixel has 4 transistors incorporated therein, the pixel requires several signal lines for its operation. Typically, such pixel has a reset line, i.e., the reset gate bus 120, a charge transfer line, i.e., the transfer gate bus 112, and an address line, i.e., the address gate bus 121, in a row direction and the Vdd line 117 and a Vout line, i.e., the pixel column bus 116, in a column direction. Although it is possible to share some of these lines and corresponding transistors between neighboring pixels, this sharing may generate other complications related to intra-pixel interconnecting lines. The increased number of row and column lines tends to consume a valuable pixel area, and thus, often reduces the pixel active area that could otherwise be used for charge storage and light sensing.